1. Field of the Invention
The present invention relates to memory cell devices, and more particularly to multi-level threshold programming method for such devices so that precise charge placement is achieved with no, or minimal, overshoot of the threshold voltage, and relatively small device overhead requirements.
2. Description of Related Art
Multi-level threshold programming of memory cells and then like is being used by many developers to increase the amount of data which can be stored in a memory device. For instance, instead of two threshold states being used to store "on" or "off" data levels in the memory cell, a larger number of threshold states are now being used and sensed as separate data levels. This allows for an increased data storage for a given amount of memory.
In order to achieve multi-level threshold programming of such memory cells, a precise charge placement is one of the main requirements. In particular, it is important to program the memory device so that no significant overshoot of the threshold voltage occurs, as overshoot might be erroneously interpreted as a subsequent data level by the sensing device. As the precision of the charge placement is increased, then significantly more voltage levels might be used with a single memory cell, thereby increasing the relative density of data storage.
Many prior arrangements and programming techniques have been proposed for multi-level threshold programming of memory cells. One such technique involves the steps of programming the memory cell and then verifying the programmed level thereafter (referred to as "program and verify"). Variations of the program and verify technique are disclosed in U.S. Pat. Nos. 5,293,560 and 5,218,569. Yet another technique involves self-convergence, wherein the desired programmed voltage level will be established by using current or voltage sensing at some point in the device to cease further programming of the device. This eliminates the need for verification of each programmed level. Examples of such self-convergence techniques are disclosed in U.S. Pat. Nos. 5,566,111 and 5,712,815.
One problem which occurs with both such techniques is that during programming, while a programmed condition is approaching a desired level, the threshold voltage of the programmed cell is shifted in coarse and uneven increments from a low level to a high level, or vice versa. This will generally cause the threshold voltage distribution to be relatively wider than desired for multi-level cell programming. Some solutions to this problem include the following: using a controlled pulse width for the gate voltage program pulse; using a smaller voltage step for each subsequent program pulse applied to the gate; and/or using more accurate reference voltage comparators. Each of these solutions involves tradeoffs in device cost and programming speed.
Still another factor which will influence the programming and establishment of working multi-level threshold voltages in a memory cell is the series resistance effect as described in U.S. Pat. No. 5,422,845. This patent proposes the solution of adding one or more resistors between the ground contact and the ground. The result of such a solution is a significant increase in device overhead as resistors generally require a large area for formation on semiconductor layouts.
Hence, it is desirable to provide a memory cell device arrangement and programming method which will provide desirably narrow distribution of multi-level threshold voltages, but without requiring costly and precise control of the gate programming pulse width and/or voltage step, or additionally require increased use of peripheral device such as comparators, resistors, and the like.